The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of several gigahertz (GHz), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been an ongoing pressure to further miniaturize the individual circuit features within an integrated circuit and packaging substrate, such as a microprocessor or a chip set component or the like.
There are many different features within an integrated circuit packaging substrate. One feature is a via. An integrated circuit packaging substrate contains several levels of circuitry. A via is a vertical opening lined with a conductive material that is used to connect a conductor trace on one layer to the next layer. Currently, a via includes a single electrical path. Therefore, if there are multiple electrical paths between a first layer within a device to a second layer within a device, there are a corresponding number of vias. A via can also provide a conductive path from a layer within a device, such as an integrated circuit, to an exterior surface.
The description set out herein illustrates the various embodiments of the invention, and such description is not intended to be construed as limiting in any manner.